The main objective of SAFEPOWER is to enable the development of cross-domain mixed-criticality systems with low power, safety and security requirements by means of the following key contributions:
1. The definition and development of a cross-domain mixed-criticality and low power reference architecture upon multicore/heterogeneous processors, as shown in Figure 1. The SAFEPOWER architecture will ensure the properties of power/energy/temperature awareness in combination with real-time support, time and space partitioning, reliability and security and provide the foundation for the development of applications (e.g., railway, aerospace), while abstracting from the details from the underlying implementation technologies.
2. The definition, implementation and demonstration of a set of mixed-criticality compliant low-power techniques and power management procedures that can be used in the development of mixed criticality Critical Real Time Embedded Systems (CRTES) mixed criticality CRTES with safety and security requirements.
3. The development of platforms and tools to enable and facilitate the development of low power mixed criticality CRTES, including software and hardware components:
- A Printed Circuit Board (PCB) implementation consisting of domain specific FPGAs/SoCs that can be plugged on a main board which enables the observability of power consumption and timing through dedicated measurement circuits
- A virtual platform environment for the early analysis, simulation, complexity-management and verification of potential low-power mixed criticality solutions.
- An Embedded Hypervisor to facilitate the integration and implementation of low power services (communication services, fault-tolerance services, low power load scheduling, diagnostic services) into mixed criticality systems.
The external assessment with respect to safety certification standards (e.g., IEC-61508) of the certifiable subset of the architecture and the power management techniques in order to pave the way towards the early adoption of the technology for the development of mixed criticality CRTES with safety requirements.
The definition and implementation of built-in security mechanisms that support the safety and low-power management of the system (e.g., authenticity, availability). These contributions will, for the first time until now, enable the use of low-power features in mixed critical embedded systems with no or at least controllable impact on safety and security features. This will enable the development of low power mixed criticality CRTES under the strict safety requirements imposed by current safety standards (e.g., IEC-61508).